Hardware design, validated at every step

Upload a netlist for expert review, or describe a board from scratch. PromptPCB extracts every datasheet, cross-references every pin, simulates every rail, and catches the defects that cost you a respin.

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Proven

69 defects found.

Every one caught before fab — saving weeks of reorder turnaround and thousands of dollars in scrapped boards. These are real defects from real designs, not theoretical.

Output capacitor underrated. Regulator stability requires minimum ESR and capacitance — board would brown-out under load.
MCU power pin not connected. Chip would never boot — invisible on a schematic review, caught by pin-level datasheet audit.
Boot pins floating. Microcontroller would enter wrong boot mode on power-up. Strapping pins must be defined.
0Boards reviewed
0Defects found
0Warnings

From sentence to shipping-ready board

Jump in wherever you are. Describe a board from scratch at Design, upload an existing netlist to Validate, or drop a design in to Simulate. Every stage checks before the next begins — failures loop back automatically, with no silent errors.

Start here
01
Design
Architect circuit from description
02
Source
Real parts, datasheets extracted
Start here
03
Validate
Expert review against datasheets
Start here
04
Simulate
Verify every electrical spec
05
Place & Route
Layout, traces, and DRC
06
Gerbers
Manufacturing-ready output
Why PromptPCB

Grounded results, not guesses

PromptPCB pairs state-of-the-art AI models with a purpose-built suite of engineering tools and custom hardware data structures — netlists, footprints, pin maps, datasheet tables, power-rail graphs. Every decision is grounded in real data, not generated from memory.

An AI model on its own

  • Hallucinates part numbers that don't exist
  • Guesses pin functions with no datasheet to read
  • Can't verify stock or footprint availability
  • "It should work" — no simulation, no proof
  • No DRC, layout, or manufacturing files
  • Still needs an engineer to validate everything

PromptPCB: models + tools + real data

  • Frontier models orchestrated across a full suite of EE tools
  • Structured netlists, pin maps & power rails the model can reason over
  • Reads the actual datasheet for every IC — pins, ratings, tables
  • Every part grounded in real JLCPCB stock and footprints
  • SPICE-level simulation with a zero-warnings policy
  • Auto-placement, routing, DRC, and gerber export
  • 20-point expert review catches what simulation misses
Simulation

Not just schematics. Physics simulation.

DC analysis, transient simulation, thermal heatmap, and live oscilloscope traces — all running on the actual circuit before you fab.

V
Every voltage rail verified against datasheet specs
T
Thermal heatmap shows hotspots before you power on
~
Oscilloscope traces for transient behavior and timing
I
Current flow visualization across every trace
LED blinking 1Hz
Thermal heatmap
Output

From layout to manufacturing files.

Copper traces, component placement, silkscreen — all generated and validated. Export Gerbers, BOM, and pick-and-place CSV.

Two products

Design from scratch, or review what you have

Whether you're starting from a sentence or uploading an existing netlist, every board gets the same rigorous validation pipeline.

Full automation BETA

Board Design

Describe a circuit in plain English. We architect, source, simulate, place, route, and validate — then hand you manufacturing-ready gerbers. Beta access for prototypes and concept designs.

  • AI-generated architecture from a sentence
  • Real JLCPCB parts, verified stock & footprints
  • Circuit simulation with zero-warnings policy
  • Auto-placement, routing, and DRC
  • 20-point expert design review
  • Gerber output, ready to order
  • Unlimited revisions
Starting at $499 per project
Start designing
Existing designs

Board Review

Upload your KiCad, EasyEDA, or Altium netlist. We extract every datasheet, cross-reference every pin, and deliver a detailed design review.

  • Upload any netlist format
  • Every IC datasheet extracted & analyzed
  • Powered by Claude, Gemini, or GPT
  • Voltage margins, decoupling, ESD, protocols
  • Pin-level compliance checking
  • Results in ~5 minutes
  • Only charged if review completes
$149 per review · up to 100 components
Start reviewing
Recent reviews

See what we catch

RK3588S Single Board Computer

330 components. 8-layer HDI. 12+ power rails. Octa-core with 6 TOPS NPU. Designed from a sentence, validated end-to-end, manufactured at JLCPCB.

Full Linux SBC from a prompt

Every part sourced from JLCPCB stock. Every pin connection validated against datasheets. Every power rail simulated. This is what automated hardware design looks like at scale.
330
Components
8-layer
HDI stackup
12+
Power rails
85×56mm
RPi form factor
RK3588S 4×A76 + 4×A55, Mali-G610, 6T NPU
8GB LPDDR4X + 32GB eMMC 5.1 storage
RK806 PMIC 10 buck + 2 LDO rails, full sequencing
USB-C PD CH224K sink, MP2315 5V buck, reverse protection
Connectivity GbE (RTL8211F), WiFi/BT, USB 3.0, HDMI 2.1
Expansion 40-pin GPIO, MIPI-CSI camera, PCIe
What gets checked

Every critical design parameter

Transistor biasingVerify every FET/BJT has correct gate/base bias and pull-down connections
Power domain isolationDetect unintended shorts between voltage rails through 0R or direct wiring
Voltage marginsCross-reference abs max ratings against actual supply voltages including transients
Required componentsConfirm every datasheet-required cap, resistor, and external component exists
Open-drain outputsVerify external pull-ups on all open-drain and open-collector pins
Feedback dividersCheck regulator math against the reference voltage from the datasheet
Boot/strapping pinsConfirm all mode-select, address, and boot pins are properly defined
NC pin complianceVerify no-connect pins are unconnected and pin functions match datasheets
ESD/TVS protectionCheck for missing protection on externally-exposed connectors and high-energy rails
Decoupling & bypassingConfirm every IC power pin has proper decoupling (type, ESR, placement)
Protocol complianceI2C pull-ups, CAN termination, USB series resistors, SPI/UART wiring
Signal integrityTrace impedance, crosstalk, return paths, and high-speed routing validated
Level translationCheck voltage translation between different logic domains is correctly implemented
Crystal loadingVerify oscillator load caps match crystal specifications
Thermal analysisPower dissipation, copper pours, and thermal relief validated against limits
Enable defaultsCheck that enable pins default to safe states based on internal pull-up/down behavior
DRC complianceClearance, annular ring, minimum trace width, and drill sizing verified
Manufacturing readinessGerber output validated for JLCPCB/PCBWay constraints before ordering
FAQ

Questions engineers ask

What about my IP? Will my designs train your AI?

No. Your designs are never used for training. All files are processed in isolated sessions and deleted after review. You can request full deletion at any time. We use third-party LLMs (Claude, Gemini, GPT) with their enterprise APIs — none of them train on your data either.

What netlist formats do you support?

KiCad (.net, .kicad_sch), EAGLE (.sch / project .zip), EasyEDA JSON, Altium (.SchDoc / .NetList), and screenshot-based capture. If you have a schematic image, we can parse it. Upload any format and we'll detect it automatically.

What if the review finds nothing wrong?

You still get the full report — verified checks, component analysis, and datasheet cross-references. A clean review is valuable confirmation. You're only charged if the review completes successfully.

How is this different from ERC in KiCad?

ERC checks electrical rules. We check against actual datasheets — is this capacitor the right value per the regulator's datasheet? Is this boot pin configured for the right mode? Are the abs max ratings respected? Things ERC can't see.

Can I use this for production boards?

The review product is production-ready today — engineers use it to catch defects before fab. The design tool (Board Design) is in beta. We recommend using it for prototypes and validating critical sections with your own review before production runs.

How long does a review take?

Typically 2-5 minutes for boards under 100 components. Larger boards (200+) may take up to 10 minutes. You'll see real-time progress as each datasheet is extracted and each check runs.

Live demo

Watch a full pipeline run

ESP32-DevKit-Lipo — full pipeline
45 components · 7 stages · all checks passed Try it free →
Your IP stays yours. Designs are never used for training.
Only pay if it works. Failed reviews are free.
Delete anytime. Full data removal on request.
Pricing

Start per board. Scale with team plans.

Engineering-grade PCB review and design automation. Your first review is free — no credit card. Upgrade when you're ready to validate real boards before fabrication.

Board Design BETA

$499 /project
Starting price. Prototype & concept designs only.
  • Architected from a sentence
  • Real JLCPCB parts & footprints
  • Simulated, placed, routed, DRC
  • Manufacturing-ready gerbers
  • Complex boards quoted custom
Start designing

Team

$999 /month
For teams reviewing multiple boards.
  • 10 board reviews / month
  • Shared team dashboard
  • Review history & reports
  • Priority processing
  • +$99/review over quota
Contact sales

Enterprise

$12K+ /year
For recurring boards, sensitive IP, or custom validation.
  • Volume review credits
  • Custom review templates
  • Private deletion policy
  • Procurement constraints
  • Direct support
Contact sales
A freelance EE bills $300+ for a 100-part review — 4–8 hours of work. PromptPCB delivers it in minutes.
$300+
The team

Built by engineers, for engineers

Devin Willis
Devin Willis
Co-founder
Founder-engineer building AI-native workflows for hardware design. CTO of PromptPCB, leading hardware engineering, circuit simulation, and embedded systems development. Graduated Summa Cum Laude from the University of Florida with a dual degree in Electrical Engineering and Management, and a UF track and field athlete. Previously Director of Engineering at Golden Hour Medical, leading development of the AutoTQ — an automated pneumatic tourniquet system — owning the complete electronics, firmware, app design, and mechanical integration from concept to market-ready medical device. Co-inventor on U.S. Patent No. 12,070,229 B1. Built a portfolio of hardware products spanning industries: TQStation (emergency-response tourniquet station), ReefVision (deep-learning edge camera for marine robotics), high-performance motor controllers, and agricultural automation systems. Earlier research includes neuroscience instrumentation with the Max Planck Institute and genomics imaging at FAU Honors College. Discovery 3M Young Scientist Top 10 finalist. Thinks every board should work on the first spin.
Scooter Willis
Scooter Willis, Ph.D.
Co-founder
Co-founder and Chief Executive Officer of Corben. His career spans three decades at the leading edge of emerging technologies, with technical and executive roles across enterprise systems, computational biology, oncology genomics, deep learning, embedded systems, robotics, and applied AI. He holds a Ph.D. in Computer Engineering with a Bioinformatics specialization and an MBA in Entrepreneurship for Engineers and Scientists, both from the University of Florida, where he previously served as student body president. He is the senior author of BioJava, an open-source bioinformatics framework named by Oracle's Java Magazine to its list of the 25 greatest Java applications ever written and still in active research use worldwide. Scooter has served on the IEEE Computer Society editorial board, on the University of Florida Alumni Association board of directors, and as co-founder of a 501(c)(3) educational-robotics non-profit serving at-risk youth in South Florida.
PromptPCB — AI-first hardware design automation
Grove Park, Florida